The present invention relates generally to semiconductor devices and the abrication thereof and, more particularly, to an semiconductor-on-insulator (SOI) MOSFET having damaged regions to enhance device performance and a method of abrication.
A pervasive trend in modern integrated circuit manufacture is to produce semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), that are as small as possible. In a typical MOSFET, a source and a drain are formed in an active region of a semiconductor layer by implanting N-type or P-type impurities in the layer of semiconductor material. Disposed between the source and the drain is a channel (or body) region. Disposed above the body region is a gate electrode. The gate electrode and the body are spaced apart by a gate dielectric layer.
The fabrication of smaller transistors allows more transistors to be placed on a single monolithic substrate for the formation of relatively large circuit systems in a relatively small die area. Also, SOI wafers offer potential advantages over bulk wafers for the fabrication of high performance integrated circuits. Dielectric isolation and reduction of parasitic capacitance improve circuit performance, and virtually eliminate latch-up in CMOS circuits. In addition, circuit layout in SOI can be greatly simplified and packing density greatly increased if the devices are made without body contacts (i.e., if the body regions of these devices are xe2x80x9cfloatingxe2x80x9d).
However, MOSFETs formed from SOI materials can exhibit parasitic effects due to the presence of the floating body (xe2x80x9cfloating body effectsxe2x80x9d). These floating body effects may result in undesirable performance in SOI devices.
In addition, device downscaling can result in a number of performance degrading effects. In FET devices with a channel having a relatively short length, the FET can experience a number of undesirable electrical characteristics referred as short channel effects (SCE). SCE generally occur when the gate does not have adequate control over the channel region, and can include threshold voltage (Vt) roll-off, off current (loff) roll-up and drain induced barrier lowering (DIBL). As the physical dimensions decrease, SCE can become more severe. SCE is the result of intrinsic properties of the crystalline materials used in the FET devices. Namely, the band gap and built-in potential at the source/body and drain/body junctions are non-scalable with the reduction of physical device dimensions, such as a reduction in channel length.
Accordingly, there exists a need in the art for semiconductor devices, such as MOSFETs, that optimize scale and performance. There also exists a need for corresponding fabrication techniques to make those semiconductor devices.
According to one aspect of the present invention, the invention is directed to a MOSFET formed in semiconductor-on-insulator format. The MOSFET includes a source and a drain formed in a layer of semiconductor material, each of the source and the drain including an extension region and a deep doped region. A body is formed between the source and the drain and includes a first damaged region adjacent the extension of the source and a second damaged region adjacent the extension of the drain. The first and second damaged regions include defects caused by amorphization of the layer of semiconductor material. A gate electrode is disposed over the body region and is separated from the layer of semiconductor material by a gate dielectric. The gate electrode, the source, the drain and the body are operatively arranged to form a transistor.
According to another aspect of the invention, the invention is directed to a method of making a MOSFET in semiconductor-on-insulator format. The method includes providing a semiconductor-on-insulator wafer having a layer of semiconductor material disposed on an insulating layer, the insulating layer disposed on a substrate; forming a gate electrode over the layer of semiconductor material and separated from the layer of semiconductor material by a gate dielectric; implanting amorphizing ion species into the layer of semiconductor material to form a source side amorphous region and a drain side amorphous region, the amorphous regions having a depth that is less than a thickness of the layer of semiconductor material; forming an offset spacer adjacent each lateral sidewall of the gate electrode; implanting dopant ion species into the layer of semiconductor material to form a source side extension and a drain side extension, the extensions having a depth that is less than the depth of the amorphous regions; forming a sidewall spacer adjacent each offset spacer; and implanting dopant ion species into the layer of semiconductor material to form a source side deep doped region and a drain side deep doped region.